A-IQ Ready – Artificial Intelligence using Quantum measured Information for realtime distributed systems at the edge
The A-IQ Ready project aims to introduce and materialise intelligent autonomous embedded systems fit for our digital age, taking advantage of technologies like edge continuum orchestration for artificial intelligence, or distributed collaborative intelligence and quantum sensing.
Starting date: 2023
UNIFY – Compilation Abstraction and Hardware Adaption for Specialized and General-Purpose Computing Unification
The limitations of current General-Purpose Processors (GPPs) has led to a shift towards specialized architectures known as Domain-Specific Architectures (DSAs) which often lack support for general programming languages. This project aims to unify specialized and general-purpose computing through new compiler technologies and architectural innovations.
Starting date: 2023
FCT Reference: 2022.06780.PTDC
ANTAREX – Auto Tuning and Adaptivity appRoach for Energy Efficient eXascale HPC Systems
“The Exascale Problem: To reach Exascale computing (1018 FLOPs), current supercomputers must achieve an energy efficiency “quantum leap” that allows this level of computation to be done at around 20 Megawatts. This will only be possible if we can target all layers of the system, from the software stack to the cooling system. What is ANTAREX? ANTAREX proposes a holistic approach capable of controlling all the decision layers in order to implement a self-adaptive application optimized for energy efficiency.[…]”
2015 – 2018
Project Reference: 671623
Topic: FETHPC-1-2014 – HPC Core Technologies, Programming Environments and Algorithms for Extreme Parallelism and Extreme Data Applications
Call: H2020-FETHPC-2014
Funding Scheme: RIA – Research and Innovation action
Funded Under: H2020-EU.1.2.2.
Coordinator: Politecnico di Milano, Italy
Participants: Politecnico di Milano, ETH Zurich, INRIA, Universidade do Porto, CINECA, IT4Innovations, Dompé, Sygic
PRACE-6IP – PRACE 6th Implementation Phase Project
PRACE is the permanent pan-European High Performance Computing service, whose HPC experts from 25 member states provide services such as advanced training, or preparation of strategies and best practices to exploit massively parallel systems and novel architectures. In this project I have participated in the preparation of a best practices guide for heterogeneous computing in the context of HPC.
2019 – 2022
Project Type: H2020
Reference: 823767
Participants: 54 partners, including INRIA, BSC, CINECA, VSB, FEUP
PEPCC – Power efficiency and performance for embedded and HPC systems with custom CGRAs
“The goal of this project is to devise efficient techniques for dynamically mapping computations extracted from execution behavior to the resources of specialized reconfigurable accelerators. The techniques will identify at runtime the hotspots of program execution. They are then optimized and mapped to CGRAs tailored to the actual set of executing kernels. Whenever one hotspot needs to be executed, the accelerator is transparently invoked. The use of specialized CGRAs reduces resource usage and improves performance. The project will apply these concepts in the ES and HPC domains. […]”
2019 – 2021
FCT project reference: PTDC/EEI-HAC/30848/2017
Coordinator: INESC TEC
Participants: INESC TEC, INESC-ID
CONTEXTWA – Middleware and Context Inference Techniques from Data-Streams for the Development of Context-Aware Services using Mobile Devices
“The ubiquity of mobile communication devices such as smartphones enables the emergence of context-aware applications and services that proactively respond to specific user activities or situations. Context information, i.e., the specific state each user is in, allows communication providers to develop and thus offer new, added value, services for a wide range of applications such as social networking, advertising, navigation or leisure. Of growing importance are healthrelated services and applications that rely on the accurate detection of each user’s physical activity either at specific instances or throughout days or even weeks. Using this information, it is possible to discover and analyze physical activity patterns and, e.g., help individuals to lead healthier lifestyles. […]”
2016 – 2019
FCT project reference: PTDC/EEI-HAC/30848/2017
Coordinator: INESC TEC
Participants: INESC TEC, INESC-ID, Altice Labs/MEO
BESTCASE-RL8-REALTIME – Languages and tools for critical real time systems
This project addressed key challenges faced by next-generation trustworthy real-time embedded systems. My participation in this project focused on the mapping of high-level descriptions, in this case in MATLAB, to low-level performant implementations in C, for embedded systems. It also represented my first contact with the LARA technology.
2013 – 2015
NORTE-01-0124-FEDER-000062
Participants: UM, FCUP, FEUP
REFLECT – Rendering FPGAs for Multi-Core Embedded Computing
“This project will develop, implement and evaluate a novel compilation and synthesis system approach for FPGA-based platforms as outlined in the figure above. We rely on Aspect-Oriented (AO) Specifications (AOS) to convey critical domain knowledge to a mapping engine while preserving the advantages of a high-level imperative programming paradigm in early software development […]”
2010 – 2012
Project Number: 248976, FP7-ICT-2009-4
Coordination: Honeywell International Sro.
Participants: INESC-ID (Lisboa, Portugal), FEUP (Faculty of Engineering of University of Porto, Porto, Portugal), TU Delft (Technische Universiteit Delft, Delft, The Netherlands), Imperial College of Science, Technology and Medicine (London, UK), Karlsruhe Institute of Technology (KIT, Karlsruhe, Germany), ACE Associated Compiler Experts b.v. (Amsterdam, The Netherlands), Coreworks – Projetos de Circuitos e Sistemas Electrónicos S.A. (Lisboa, Portugal)
RAMTEDRA – Runtime Adaptive Mapping Techniques for Dynamically Reconfigurable Architectures
“In this project we propose to research and develop (runtime) techniques to dynamically adapt both software and hardware components according to the hardware resources available during runtime. We will research schemes for dynamic reconfiguration of computing engines coupled to a microprocessor.
2010 – 2011
Convénio FCT/DAAD 2010/2011
Participants: FEUP (Faculty of Engineering of University of Porto, Porto, Portugal), Karlsruhe Institute of Technology (KIT, Karlsruhe, Germany)
Cobaya – Closing the compilation gap between algorithms and coarse-grained reconfigurable array architectures
“This project aims at developing compiler techniques and coarse-grained reconfigurable array architectures to substantially reduce the development time in the embedded and reconfigurable computing domains achieving performance demands. Mobile Robotics will be used as the main focus of application. […]”
2007 – 2011
FCT project reference: PTDC/EEA-ELC/70272/2006
Coordinator: FEUP (Faculty of Engineering of University of Porto, Porto, Portugal) and INESC-ID
Participants: FEUP (Faculty of Engineering of University of Porto, Porto, Portugal) and INESC-ID
Amadeus – Aspects And Compiler Optimizations For Matlab System Development
“[…] This project addresses the enrichment of MATLAB with aspect-oriented extensions to include additional information (e.g., type and shape of variables) and to experiment different implementation features (e.g., different implementations for the same function, certain type binding for variables, etc.). The proposed aspects aim to configure the low-level data representation of real variables and expressions, to specifically-tailored data representations that benefit from a more efficient support by target computing engines (e.g., fixed- instead of floating-point representations). The approach also aims to help developers to introduce handlers (code triggered when certain conditions may occur and with a richer functionality than assertions) and monitoring features, and to configure function implementations. We believe aspect-oriented extensions will help system modelling, simulation, and exploration of features conceiving system implementation. One of the advantages is related to the fact that a single version of the specification can be used throughout the entire development cycle rather than maintaining multiple versions, as is currently the case. The project includes research on: aspect mining on MATLAB specifications to identify crosscutting concerns in a system, to enable migration of existing MATLAB specifications to aspect-oriented ones; type inference analysis and memory minimization techniques to generate high-performance code and to achieve highly–abstract aspects.[…].”
2007 – 2011
FCT project reference: PTDC/EIA/70271/2006
Coordinator: FEUP (Faculty of Engineering of University of Porto, Porto, Portugal) and INESC-ID
Participants: FEUP (Faculty of Engineering of University of Porto, Porto, Portugal), INESC-ID, Instituto de Desenvolvimento de Novas Tecnologias (UNINOVA/FCT/UNL), Fundação da Faculdade de Ciências e Tecnologia (FFCT/FCT/UNL), Universidade do Minho (UM)
Contacts
Email: sc.dei@fe.up.pt
Phone: (+351) 220413916 (ext. 3916)
Location
Laboratory J204
Faculdade de Engenharia da Universidade do Porto (FEUP)
Rua Dr. Roberto Frias
4200-465 Porto, Portugal