Lecture DEI Series

Date: July 26th

Time: 16:15

Room: I-105

Speaker: DEJAN S. MILOJICIC

Affiliation: Hewlett Packard Labs

Abstract

Data explosion is not coming it’s here, and it’s only getting bigger. The next stage of technology will need to accommodate unprecedented amounts of data driven by 100s of billions of devices and sensors that comprise the Internet of Things stretching our technology capabilities to the limit and beyond. At the same time, we’re operating in an increasingly insecure, unmanageable and risky environment from a technology, business and societal perspective. If we don’t find a way to change todays computing architectures, they simply won’t be able to keep up and the we won’t be able to obtain the resources needed to power and sustain them.
In this talk, I will present how Hewlett Packard Labs address these radical changes by innovating technology in the areas of photonics, silicon design, memory driven computing, security, AI, and edge. By working closely from customer requirements and focusing on HPE productization opportunities, we deliver innovation that matters. I will provide specific examples of research projects, such as unconventional architectures, programming, and accelerators, new approaches to security, etc. This way we are able to address the limits imposed by post-Mooreb s Law and the onslaught of generated data.

Short Bio

Dejan is a distinguished technologist at Hewlett Packard Labs, Palo Alto, CA (1998-) leading system software teams over 4 continents and projects with budgets of hundreds US$M. He worked at the OSF Research Institute in Cambridge, MA and at the Mihajlo Pupin Institute in Belgrade, Serbia. Milojicic received his PhD from Kaiserslautern University, Germany; and his MSc/BSc from Belgrade University, Serbia. He was a technical director of the Open Cirrus Cloud Computing Testbed, with academic, industrial and government sites in the US, Europe, and Asia. He has published 2 books and 180 papers; he has 37 granted patents. He is an IEEE Fellow (2010) and ACM Distinguished Engineer (2008). Milojicic was on 8 PhD thesis committees and taught Cloud management course at SJSU. As president of the IEEE Computer Society (2014), he started Technology Predictions, the top viewed CS news. As the industry engagement chair, he started IEEE Infrastructure’18 conference”

“Lecture DEI Series

Date: July 15th

Time: 11:00

Room: Auditório B – INESCTEC

Speaker: Cristina Silvano

Affiliation: Dept. of Electronics, Information and Bioengineering, Politecnico di Milano, Italy

Abstract

Several classes of applications can expose at runtime a set of software knobs (including application parameters and code transformations) to trade-off the quality of the results and the throughput. Resource management and application autotuning are key issues for enabling computing systems to adjust their behavior in the face of changing conditions, operating environments, usage contexts and resource availability while meeting energy-efficiency and Quality-of-Service requirements.
This talk will present dynamic autotuning techniques for the multi-objective optimization of applications to tune software knobs in an adaptive scenario to trade-off accuracy versus performance. Machine learning techniques are used to predict the system behavior based on a set of training data. The main challenge is to exploit design-time and run-time concepts to lead to an effective way of “self-aware” computing. The talk also presents the application of dynamic autotuning techniques to energy-efficient HPC systems.

Short Bio

Cristina Silvano is a Full Professor of Computer Engineering at the Politecnico di Milano, Dept. of Electronics, Information and Bioengineering. In 2017, she has been elevated IEEE Fellow “for contributions to energy-efficient computer architectures”. Her research focuses on computer architectures and Electronic Design Automation, with emphasis on power-aware design of embedded systems, design space exploration of energy-efficient computer architectures and application autotuning for manycore architectures and High-Performance Computing. She was Project Coordinator of three European projects: H2020-FET-HPC ANTAREX-671623 (2015-2018), FP7-2PARMA-248716 (2010-2013) and FP7-MULTICUBE-216693 (2008-2010). She is an active member of the scientific community and she regularly serves in several international program committees. She also organized 15 international conferences/workshops as Program Chair or General Chair. She is Associate Editor of ACM Trans. on Architecture and Code Optimization (TACO) and IEEE Trans. on Computers. She served as Independent Expert Reviewer for the European Commission and for several science foundations. Her scientific production consists of more than 160 publications.”

“Lecture DEI Series

Date: June 25th

Time: 14:00

Room: Auditório A – INESCTEC

Speaker: Walid A. Najjar

Affiliation: Department of Computer Science & Engineering University of California Riverside

Abstract

For over two decades the gap between processor and memory speeds has been the most daunting challenge in computer architecture. The advent of big data applications has exacerbated the problem. Traditional multi-core architecture mitigate memory latency through the use of massive cache hierarchies that take up over 80% of the chip area and a proportional percentage of the energy budget. However, big data applications exhibit very poor data locality and cannot benefits from large cache hierarchies. Such applications will be fully impacted by memory latency. Hardware multithreaded architectures have the ability to mask memory latency by context switching between ready threads when a memory access is performed. Classical hardware multithreaded architectures, such as barrel processors (e.g. the UltraSparc and the Cray XMT), must maintain a full state for every thread which requires a lot of resources. FPGAs allow us the opportunity to configure custom or semi-custom processing cores for specific applications.
In this talk I will describe the implementation of data processing applications on the latency masking Filament architecture using semi-custom data paths.

Short Bio

Walid A. Najjar is a Professor in the Department of Computer Science and Engineering at the University of California Riverside. His areas of research include computer architectures and compilers for parallel and high-performance computing, embedded systems, FPGA-based code acceleration and reconfigurable computing.

Walid received a B.E. in Electrical Engineering from the American University of Beirut in 1979, and the M.S. and Ph.D. in Computer Engineering from the University of Southern California in 1985 and 1988 respectively. From 1989 to 2000 he was on the faculty of the Department of Computer Science at Colorado State University, before that he was with the USC-Information Sciences Institute. He was elected Fellow of the IEEE and the AAAS.”