Cobaya: Closing The Compilation Gap Between Algorithms And Coarse-Grained Reconfigurable Array Architectures

João Manuel Paiva Cardoso, Faculdade de Engenharia da Universidade do Porto (FE/UP). €42,397.


Main Research Area
Electrical Engineering – Electronics and Computers


  • Compilers
  • Reconfigurable Computing
  • Coarse-Grained Arrays
  • FPGAs


42,397.00 €


Main Contractor
Faculdade de Engenharia da Universidade do Porto (FE/UP)
Main Research Unit
Instituto de Engenharia de Sistemas e Computadores, Investigação e Desenvolvimento em Lisboa (INESC ID/INESC/IST/UTL)


Principal Investigator
João Manuel Paiva Cardoso

Horácio Cláudio de Campos Neto
Mário Pereira Véstias
Rui Fernando da Luz Marcelino
Adriano Kaminski Sanches
João Carlos Viegas Martins Bispo

Ali Azarian


Embedded systems are playing an increasingly important role in nowadays life. They can be seen in a myriad of devices such as PDAs, cell phones, etc. New computer science disciplines have emerged focusing features and concepts related to the fact that small devices are becoming powerful mobile computing platforms. Such platforms are likely to rely on system-on-a-chip (SoCs) devices to give the required low energy consumption and computing demands. One of the most promising technologies to support SoCs are reconfigurable computing architectures (e.g., FPGAs) since they can implement single-or multi-processor software solutions together with dedicated hardware tailored to the application to be executed. Those architectures also provide the programming flexibility needed to upgrade applications during the life time of the product and to efficiently execute different applications.

Coarse-grained reconfigurable array architectures are an important SoC component. The shorter reconfiguration times and better energy and performance efficiency on mapping computational structures make coarse-gained arrays more suitable for certain applications than “gate-level” reconfigurable architectures. Coarse-grained arrays can also be an important target template for easier mapping of algorithms on complex FPGAs, as array softcores implemented by programming the FPGA resources.

Although designing reconfigurable hardware is softening, there is still the need to master digital system design in order to accomplish most requirements. However, the increasingly complexity of the architectures, the time-to-market pressures, the need for design upgrades and modifications in requirements, strongly indicate the necessity to program reconfigurable architectures at high-levels of abstraction. Efforts on compiling from software programming languages have been done for several years. However, the lack of support on FPGAs to help software compilation, their too close to gate-level basic elements, the clock frequency too dependent on place and route, seem to hamper the needed breakthrough advancements.

Bearing in mind the above referred issues, this project focuses on compiler techniques and architectural schemes that can be used to bridge the gap between software programming languages and reconfigurable computing architectures. Major research efforts on reconfigurable architectures seem to have been performed without the full attention on how algorithms are coded in software programming languages and without strong evidences about the design decisions taken. We focus on the foundations established by our previous work on a supportive environment to accomplish specific array architectures that can be coupled to a microprocessor in order to complement it with more efficient support for some computing behaviours and offering an easier path to map loop kernels to those arrays. We will make research efforts to reduce the mapping difficulties by providing the array architecture with some support for dynamic scheduling, loop control schemes, data-driven behaviour, etc. Compilation techniques targeted for array architectures will also be researched. An intermediate representation model will be researched. That model will use the dynamic reconfiguration capabilities of some FPGA devices both to program an architectural template during runtime execution of an application and to switch templates based on the application requirements. We also plan that certain resources of each architectural template can be conditionally configured, based on its usage by the task being executed.

For validating our research we will use applications from mobile robotics as they exhibit most embedded system requirements and expose many challenges not being currently addressed. Mobile robotics need high-performance, real-time behaviour, energy savings, etc. It usually demands miniaturisation, frequently leading to a SoC solution. It typically needs hardware/software co-design, since for most robotic kernels using software implementations alone does not permit to achieve the required performance.

Since an evaluation of the computational engines generated for mobile robotics algorithms require in-the-field experiences (due, e.g., to environment changes and real-time behaviour) we will use a prototype mobile robot (consisting of FPGA boards, camera, sensors, etc) to benchmark the specified application repository.

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