Rendering FPGAs for Multi-Core Embedded Computing


This project will develop, implement and evaluate a novel compilation and synthesis system approach for FPGA-based platforms as outlined in the figure above. We rely on Aspect-Oriented (AO) Specifications (AOS) to convey critical domain knowledge to a mapping engine while preserving the advantages of a high-level imperative programming paradigm in early software development and portability. We leverage AOS specifications and a set of transformations to generate an intermediate representation using an extensible mapping language (LARA). LARA specifications will allow a seamless exploration of alternative architectures and run-time adaptive strategies allowing the generation of flexible hardware cores that can be easily incorporated into larger multi-core designs. By developing schemes to specify aspects of hardware templates, required for a compiler to be able to integrate them with other hardware templates forming more powerful computing systems, will also create foundations to leverage the generation of multi-core computing systems. The overall compiler design approach is complemented with machine learning techniques to decide based on previously best known practices allowing the compiler to explore very efficiently multiple design alternatives and thus achieving better solutions otherwise not possible to be achieved at least with reasonable compiling time. In many applications (such as avionics), a model-based approach can allow the specification of the design “naturally” with inherent separation of certain aspects such as algorithm behaviour, data-types, temporal coupling, parallelism, and fault tolerance. Thus a good, and possibly close to optimal, mapping of these applications on reconfigurable processing architectures, compared to current architectures, appears very feasible if suitable efficient tooling is available. We will use AO specifications along with LARA mappings to explore the extent of such improvements.

We will evaluate the effectiveness of the proposed approach using partner-provided codes and design models used in real-life applications. This evaluation includes the development of two demonstrators, organized as a series of staged demonstrations, an avionics real-time controller algorithms evaluation and a universal audio decoder. Both these codes bring very realistic and demanding challenges that will highlight the power and impact of the base techniques and methodologies in the proposed REFLECT approach over traditional design and mapping methodologies.

Funding and Duration

3 years, 2010-01-01 to 2012-12-31


Consortium Description

Honeywell International, s.r.o (HON)
Instituto de Engenharia de Sistemas e Computadores – Investigação e Desenvolvimento em Lisboa (INESC-ID)
Faculdade de Engenharia da Universidade do Porto (FEUP)
Delft University of Technology Computer Engineering Laboratory (TU Delft)
Karsruhe Institute Technology (KIT)
Imperial College of Science Technology and Medicine (IC)
Associated Compiler Experts b.v. (ACE)
Coreworks – Projectos de Circuitos e Sistemas Electrónicos s.a (CW)

Industrial Advisory Board

Altera Corp., USA
EADS Innovation Works, Germany
Infineon Technologies AG, Germany
NXP Semiconductors, Eindhoven, The Netherlands


Project Coordinator:
Zlatko Petrov

Project Scientific Coordinator:

João Manuel Paiva Cardoso
Phone: +351 916629046

Pedro C. Diniz (INESC-ID)

RAMTEDRA – Runtime Adaptive Mapping Techniques for Dynamically Reconfigurable Architectures

Duration: 2 years, May. 2010


In this project we propose to research and develop (runtime) techniques to dynamically adapt both software and hardware components according to the hardware resources available during runtime. We will research schemes for dynamic reconfiguration of computing engines coupled to a microprocessor. Specifically, we will use a regular expression and a sorting computing hardware engine to analyse and evaluate the potential of software/hardware dynamic adaptation in order to use more hardware resources whenever higher performance is required and hardware space is available. We will research and develop new dynamic, partial, reconfiguration schemes to specialise domain-specific architectures in order to improve resource usage and maximum operating clock frequencies.

The major scientific goals of this project are:

  • To research methods for both software and hardware runtime adaptations. This will be the first time to be addressed, as far as we know, and will consists on novel scientific achievements;
  • To continue researching dynamic reconfiguration techniques to complement automatic generation of strategies based on a set of programmable, hardware templates;
  • To understand better the impact of dynamic reconfiguration when dealing with hardware/software systems. The use of a sorting machine and a machine to accelerate evaluation of large sets of regular expressions will be used to test and apply the main techniques.


  • Institut für Technik der Informationsverarbeitung (ITIV), Karlsruhe Institute of Technology (KIT), Karlsruhe, Germany
  • Faculty of Engineering, University of Porto, Porto, Portugal


Bilateral cooperation: FCT/DAAD 2010/2011, under Ref. daad124412622223295


João Manuel Paiva Cardoso

Associate Professor

Department of Informatics Engineering (DEI), Faculty of Engineering,

University of Porto,

Porto, Portugal


Skype: jmcardo

Phone: +351 916629046


Faculdade de Engenharia da Universidade do Porto (FEUP)

Rua Dr. Roberto Frias

4200-465 Porto Portugal

Cobaya: Closing The Compilation Gap Between Algorithms And Coarse-Grained Reconfigurable Array Architectures

João Manuel Paiva Cardoso, Faculdade de Engenharia da Universidade do Porto (FE/UP). €42,397.


Main Research Area
Electrical Engineering – Electronics and Computers


  • Compilers
  • Reconfigurable Computing
  • Coarse-Grained Arrays
  • FPGAs


42,397.00 €


Main Contractor
Faculdade de Engenharia da Universidade do Porto (FE/UP)
Main Research Unit
Instituto de Engenharia de Sistemas e Computadores, Investigação e Desenvolvimento em Lisboa (INESC ID/INESC/IST/UTL)


Principal Investigator
João Manuel Paiva Cardoso

Horácio Cláudio de Campos Neto
Mário Pereira Véstias
Rui Fernando da Luz Marcelino
Adriano Kaminski Sanches
João Carlos Viegas Martins Bispo

Ali Azarian


Embedded systems are playing an increasingly important role in nowadays life. They can be seen in a myriad of devices such as PDAs, cell phones, etc. New computer science disciplines have emerged focusing features and concepts related to the fact that small devices are becoming powerful mobile computing platforms. Such platforms are likely to rely on system-on-a-chip (SoCs) devices to give the required low energy consumption and computing demands. One of the most promising technologies to support SoCs are reconfigurable computing architectures (e.g., FPGAs) since they can implement single-or multi-processor software solutions together with dedicated hardware tailored to the application to be executed. Those architectures also provide the programming flexibility needed to upgrade applications during the life time of the product and to efficiently execute different applications.

Coarse-grained reconfigurable array architectures are an important SoC component. The shorter reconfiguration times and better energy and performance efficiency on mapping computational structures make coarse-gained arrays more suitable for certain applications than “gate-level” reconfigurable architectures. Coarse-grained arrays can also be an important target template for easier mapping of algorithms on complex FPGAs, as array softcores implemented by programming the FPGA resources.

Although designing reconfigurable hardware is softening, there is still the need to master digital system design in order to accomplish most requirements. However, the increasingly complexity of the architectures, the time-to-market pressures, the need for design upgrades and modifications in requirements, strongly indicate the necessity to program reconfigurable architectures at high-levels of abstraction. Efforts on compiling from software programming languages have been done for several years. However, the lack of support on FPGAs to help software compilation, their too close to gate-level basic elements, the clock frequency too dependent on place and route, seem to hamper the needed breakthrough advancements.

Bearing in mind the above referred issues, this project focuses on compiler techniques and architectural schemes that can be used to bridge the gap between software programming languages and reconfigurable computing architectures. Major research efforts on reconfigurable architectures seem to have been performed without the full attention on how algorithms are coded in software programming languages and without strong evidences about the design decisions taken. We focus on the foundations established by our previous work on a supportive environment to accomplish specific array architectures that can be coupled to a microprocessor in order to complement it with more efficient support for some computing behaviours and offering an easier path to map loop kernels to those arrays. We will make research efforts to reduce the mapping difficulties by providing the array architecture with some support for dynamic scheduling, loop control schemes, data-driven behaviour, etc. Compilation techniques targeted for array architectures will also be researched. An intermediate representation model will be researched. That model will use the dynamic reconfiguration capabilities of some FPGA devices both to program an architectural template during runtime execution of an application and to switch templates based on the application requirements. We also plan that certain resources of each architectural template can be conditionally configured, based on its usage by the task being executed.

For validating our research we will use applications from mobile robotics as they exhibit most embedded system requirements and expose many challenges not being currently addressed. Mobile robotics need high-performance, real-time behaviour, energy savings, etc. It usually demands miniaturisation, frequently leading to a SoC solution. It typically needs hardware/software co-design, since for most robotic kernels using software implementations alone does not permit to achieve the required performance.

Since an evaluation of the computational engines generated for mobile robotics algorithms require in-the-field experiences (due, e.g., to environment changes and real-time behaviour) we will use a prototype mobile robot (consisting of FPGA boards, camera, sensors, etc) to benchmark the specified application repository.

Amadeus: Aspects And Compiler Optimizations For Matlab System Development

João Manuel Paiva Cardoso, Faculdade de Engenharia da Universidade do Porto (FE/UP). €106,000.


Main Research Area: Computer Engineering

Secondary Research Area: Electrical Engineering – Electronics and Computers

Compiler optimizations
System Engineering


106,000.00 €


Main Contractor
Faculdade de Engenharia da Universidade do Porto (FE/UP)

Participating Institutions
Instituto de Desenvolvimento de Novas Tecnologias (UNINOVA/FCT/UNL)
Fundação da Faculdade de Ciências e Tecnologia (FFCT/FCT/UNL)
Universidade do Minho (UM)
Main Research Unit
Instituto de Engenharia de Sistemas e Computadores, Investigação e Desenvolvimento em Lisboa (INESC ID/INESC/IST/UTL)


Principal Investigator
João Manuel Paiva Cardoso
João Alexandre Baptista Vieira Saraiva
João Miguel Lobo Fernandes
Luis Filipe dos Santos Gomes
Miguel Jorge Tavares Pessoa Monteiro
Rui Manuel Carvalho Pais
Anikó Katalin Horváth da Costa
Pedro Nuno Ferreira da Rosa da Cruz Diniz
Pedro Miguel Ribeiro Martins
Tiago Diogo Ribeiro de Carvalho


MATLAB is a high-level, interpreted, domain-specific language (DSL), mainly based on matrix data types and operations on them. The MATLAB environment, the richness of the language, the existence of domain-oriented packages, and the associated software tools, make the language one of the preferred choices to model and simulate complex systems (it is widely used in scientific computing, control systems, signal and image processing, system engineering, etc.). More than 800 books dedicated to MATLAB attest to its wide adoption.

Suitable MATLAB properties include no need to declare variables (floating-point double precision representation is the default data type), operator overloading, function polymorphism and dynamic type specialisation. However, tasks such as exploiting non-uniform fixed-point representations, monitoring certain variables during a timing window, or including handlers to watch specific behaviours are extremely cumbersome, error-prone and tedious. Each time these features are necessary, invasive changes on the original code, as well as insertion of new code need to be performed. This problem is felt in other implementation issues as well, since MATLAB can be regarded as a specification rather than an implementation language. Other open issues are related to efficient automatic synthesis of MATLAB specifications to a software language or a hardware description language.

This project addresses the enrichment of MATLAB with aspect-oriented extensions to include additional information (e.g., type and shape of variables) and to experiment different implementation features (e.g., different implementations for the same function, certain type binding for variables, etc.). The proposed aspects aim to configure the low-level data representation of real variables and expressions, to specifically-tailored data representations that benefit from a more efficient support by target computing engines (e.g., fixed- instead of floating-point representations). The approach also aims to help developers to introduce handlers (code triggered when certain conditions may occur and with a richer functionality than assertions) and monitoring features, and to configure function implementations. We believe aspect-oriented extensions will help system modelling, simulation, and exploration of features conceiving system implementation. One of the advantages is related to the fact that a single version of the specification can be used throughout the entire development cycle rather than maintaining multiple versions, as is currently the case. The project includes research on:

  • aspect mining on MATLAB specifications to identify crosscutting concerns in a system, to enable migration of existing MATLAB specifications to aspect-oriented ones;
  • type inference analysis and memory minimization techniques to generate high-performance code and to achieve highly–abstract aspects.