Rendering FPGAs for Multi-Core Embedded Computing


This project will develop, implement and evaluate a novel compilation and synthesis system approach for FPGA-based platforms as outlined in the figure above. We rely on Aspect-Oriented (AO) Specifications (AOS) to convey critical domain knowledge to a mapping engine while preserving the advantages of a high-level imperative programming paradigm in early software development and portability. We leverage AOS specifications and a set of transformations to generate an intermediate representation using an extensible mapping language (LARA). LARA specifications will allow a seamless exploration of alternative architectures and run-time adaptive strategies allowing the generation of flexible hardware cores that can be easily incorporated into larger multi-core designs. By developing schemes to specify aspects of hardware templates, required for a compiler to be able to integrate them with other hardware templates forming more powerful computing systems, will also create foundations to leverage the generation of multi-core computing systems. The overall compiler design approach is complemented with machine learning techniques to decide based on previously best known practices allowing the compiler to explore very efficiently multiple design alternatives and thus achieving better solutions otherwise not possible to be achieved at least with reasonable compiling time. In many applications (such as avionics), a model-based approach can allow the specification of the design “naturally” with inherent separation of certain aspects such as algorithm behaviour, data-types, temporal coupling, parallelism, and fault tolerance. Thus a good, and possibly close to optimal, mapping of these applications on reconfigurable processing architectures, compared to current architectures, appears very feasible if suitable efficient tooling is available. We will use AO specifications along with LARA mappings to explore the extent of such improvements.

We will evaluate the effectiveness of the proposed approach using partner-provided codes and design models used in real-life applications. This evaluation includes the development of two demonstrators, organized as a series of staged demonstrations, an avionics real-time controller algorithms evaluation and a universal audio decoder. Both these codes bring very realistic and demanding challenges that will highlight the power and impact of the base techniques and methodologies in the proposed REFLECT approach over traditional design and mapping methodologies.

Funding and Duration

3 years, 2010-01-01 to 2012-12-31


Consortium Description

Honeywell International, s.r.o (HON)
Instituto de Engenharia de Sistemas e Computadores – Investigação e Desenvolvimento em Lisboa (INESC-ID)
Faculdade de Engenharia da Universidade do Porto (FEUP)
Delft University of Technology Computer Engineering Laboratory (TU Delft)
Karsruhe Institute Technology (KIT)
Imperial College of Science Technology and Medicine (IC)
Associated Compiler Experts b.v. (ACE)
Coreworks – Projectos de Circuitos e Sistemas Electrónicos s.a (CW)

Industrial Advisory Board

Altera Corp., USA
EADS Innovation Works, Germany
Infineon Technologies AG, Germany
NXP Semiconductors, Eindhoven, The Netherlands


Project Coordinator:
Zlatko Petrov

Project Scientific Coordinator:

João Manuel Paiva Cardoso
Phone: +351 916629046

Pedro C. Diniz (INESC-ID)

Posted in Project.