Dealing with memory latency in the age of big data

Lecture DEI Series

Date: June 25th

Time: 14:00

Room: Auditório A – INESCTEC

Speaker: Walid A. Najjar

Affiliation: Department of Computer Science & Engineering University of California Riverside

Abstract

For over two decades the gap between processor and memory speeds has been the most daunting challenge in computer architecture. The advent of big data applications has exacerbated the problem. Traditional multi-core architecture mitigate memory latency through the use of massive cache hierarchies that take up over 80% of the chip area and a proportional percentage of the energy budget. However, big data applications exhibit very poor data locality and cannot benefits from large cache hierarchies. Such applications will be fully impacted by memory latency. Hardware multithreaded architectures have the ability to mask memory latency by context switching between ready threads when a memory access is performed. Classical hardware multithreaded architectures, such as barrel processors (e.g. the UltraSparc and the Cray XMT), must maintain a full state for every thread which requires a lot of resources. FPGAs allow us the opportunity to configure custom or semi-custom processing cores for specific applications.
In this talk I will describe the implementation of data processing applications on the latency masking Filament architecture using semi-custom data paths.

Short Bio

Walid A. Najjar is a Professor in the Department of Computer Science and Engineering at the University of California Riverside. His areas of research include computer architectures and compilers for parallel and high-performance computing, embedded systems, FPGA-based code acceleration and reconfigurable computing.

Walid received a B.E. in Electrical Engineering from the American University of Beirut in 1979, and the M.S. and Ph.D. in Computer Engineering from the University of Southern California in 1985 and 1988 respectively. From 1989 to 2000 he was on the faculty of the Department of Computer Science at Colorado State University, before that he was with the USC-Information Sciences Institute. He was elected Fellow of the IEEE and the AAAS.”

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