A palestra intulada “Fifty Years of the Algorithm Selection Problem: John Rice’s Enduring Legacy” será apresentada no dia 27 de maio, às 11:00, na sala B008, como a moderação do Prof. Carlos Soares (DEI).

Sobre a Palestra:

“The seminal paper “The Algorithm Selection Problem” by John Rice was published 50 years ago. This paper formalizes the problem of selecting the best algorithm for a given problem, which is important in Machine Learning, Optimization and many areas of Computer Science. In this talk, I discuss the paper, its impact and challenges it raises which are still open today.”

Sobre a Oradora:

“Kate Smith-Miles AO FAA is Pro Vice-Chancellor (Research Capability) and a Melbourne Laureate Professor in the School of Mathematics and Statistics at The University of Melbourne. She is also Director of the ARC Training Centre in Optimisation Technologies, Integrated Methodologies, and Applications (OPTIMA). She has previously held a five year Laureate Fellowship from the Australian Research Council with a Georgina Sweet Award, and has held positions as President of the Australian Mathematical Society (2016-2018), a member of the Australian Research Council College of Experts (2017-2019), and Associate Dean (Enterprise and Innovation) in the University’s Faculty of Science (2019-2023). Prior to joining The University of Melbourne in September 2017, she was Professor of Applied Mathematics at Monash University, where she was also Head of the School of Mathematical Sciences (2009-2014), and inaugural Director of the Monash Academy for Cross & Interdisciplinary Mathematical Applications (MAXIMA) from 2013-2017. She was also previously Head of the School of Engineering and Information Technology at Deakin University (2006-2009) with a Chair in Engineering. She obtained her first Professorship in Information Technology at Monash University, where she worked from 1996-2006. Professorships in three disciplines (mathematics, engineering, and information technology) have given her an interdisciplinary breadth reflected in much of her research.”

A palestra intitulada “O Turing Award de 2025: Partilha de Chaves Secretas usando Mecânica Quântica” será apresentada no dia 3 de junho, às 14:30, na sala B004, com a moderação da Prof. Ana Paiva (DEI).

Sobre a Palestra:

O Turing Award de 2025 foi atribuído este ano a Charles H. Bennet e Gilles Brassard, pelo seu trabalho em criptografia quântica. No seu artigo de 1984, introduziram o famoso Protocolo BB84, onde mostraram como duas pessoas podem partilhar uma chave criptográfica secreta. A segurança deste protocolo é garantida pelas próprias leis da física quântica. Nesta palestra, o Orador explicará este protocolo e o seu significado. Não são necessários conhecimentos profundos de mecânica quântica.

Sobre o Orador:

Sagar Silva Pratapsi é Professor Auxiliar do Departamento de Engenharia Informática da FEUP. É investigador em computação e informação quântica, com um foco em princípios fundamentais da mecânica quântica, controlo de sistemas quânticos, e alguns algoritmos.
Doutorou-se pelo Instituto Superior Técnico em 2024 e foi Professor Auxiliar Convidado na Universidade de Coimbra até 2026, onde leccionou sobre computação e informação quânticas. Foi também estudante investigador convidado na Universidade de Califórnia, Berkeley em 2024, financiado pela Fundação Luso-Americana para o Desenvolvimento, e estudante visitante da Universade de Maryland em Baltimore em 2023, no âmbito de uma bolsa de doutoramento financiada pela Fundação “la Caixa”. Antes do doutoramento, trabalhou como Research Analyst no Banco Central Europeu. Teve também outros reconhecimentos, como bolseiro do programa Novos Talentos da Matemática, da Fundação Calouste Gulbenkian, e é medalhado das Olimpíadas Internacionais da Física.

A palestra intitulada “Hybrid neural systems: neuromorphic computing for real-time control of brain activity“, será apresentada no dia 15 de junho, pelas 14:00, na sala I-105. A moderação ficará a cargo de Henrique Lopes Cardoso (DEI).

Sobre a Palestra:

“The brain is a powerful model for fast, adaptive and energy-efficient information processing. Translating these principles into computing systems is a major challenge with direct relevance for the next generation of intelligent neural interfaces. In this talk I will present work from my research group where we developed a hybrid neural system combining biological neurons with neuromorphic hardware, where artificial spiking neurons process ongoing brain activity in real time. By converting biological signals into spike-based representations, we trained spiking neural networks (SNNs) to identify short-lived electrophysiological patterns and deployed them on neuromorphic hardware. This system was integrated with open-source electrophysiology tools to create a closed-loop pipeline capable of detecting ongoing brain states and triggering targeted stimulation with low latency. Using this approach, we show that hybrid systems linking artificial and biological neurons can support real-time interaction with living neural circuits. These results provide a proof-of-concept for accessible neuromorphic neural interfaces and open new possibilities for adaptive, low-power and biologically inspired computing technologies.”

Sobre o Orador:

Paulo Aguiar é licenciado em Física (Universidade de Lisboa, PT) e doutorado em Neurociência Computacional pelo Instituto de Computação Adaptativa e Neural (Universidade de Edimburgo, Reino Unido). Desde 2016, dirige o Laboratório de Neuroengenharia e Neurociência Computacional (i3S-UPorto, PT). O seu grupo adota uma abordagem ascendente, centrando-se na compreensão de como os circuitos neurais processam e armazenam informação. A equipa combina conhecimentos especializados em neurobiologia, métodos analíticos avançados e modelos computacionais, para revelar e reparar a função neural. Já foi (co)investigador principal/líder de tarefa em mais de 20 projetos de investigação nacionais e internacionais obtidos através de concursos.

A palestra intitulada “nanoML: Pushing the Limits of Edge AI with Weightless Neural Networks“, será apresentada pela Prof. Lizy Kurian John (University of Texas at Austin) no dia 6 de maio, às 14:30, na sala I-105. A sessão será moderada pelo Prof. Pedro Diniz (DEI).

Sobre a Palestra:

“Mainstream artificial neural network models, such as Deep Neural Networks (DNNs) are computation-heavy and energy-hungry. Weightless Neural Networks (WNNs) are natively built with RAM-based neurons and represent an entirely distinct type of neural network computing compared to DNNs. WNNs are extremely low-latency, low-energy, and suitable for efficient, accurate, edge inference. The WNN approach derives an implicit inspiration from the decoding process observed in the dendritic trees of biological neurons, making neurons based on Random Access Memories (RAMs) and/or Lookup Tables (LUTs) ready-to-deploy neuromorphic digital circuits. WNNs are a natural fit for edge AI due to the low area, energy and latency properties offered by them. This talk will describe the state of the art of Weightless Neural Networks, and their applications for edge inferencing.”

Sobre a Oradora:

“Lizy Kurian John is Truchard Foundation Chair in Engineering at the University of Texas at Austin. Her research interests include workload characterization, performance evaluation, and high performance architectures for emerging workloads. She is recipient of many awards including Joe J. King Professional Engineering Achievement Award (2023), and The Pennsylvania State University Outstanding Engineering Alumnus Award (2011). She has authored 3 books and has edited 4 books including a book on Computer Performance Evaluation and Benchmarking. She holds 18 US patents and is an IEEE Fellow (Class of 2009), ACM Fellow, AAAS Fellow and Fellow of the National Academy of Inventors (NAI).”

Agradecimentos: Lizy K. John é atualmente especialista Fulbright. A sua investigação é financiada, em parte, pelas bolsas n.º 2326894 e n.º 2425655 da Fundação Nacional de Ciência dos Estados Unidos (NSF), pela Semiconductor Research Corporation (SRC) task 3148.001 e pela bolsa do Programa de Aceleração de Investigação Aplicada da NVIDIA.

A palestra intitulada “When AI meets Performance Engineering: Challenges and Opportunities“, será apresentada pela Prof. Lizy Kurian John (University of Texas at Austin), no dia 29 de abril, às 14:30, na sala L119 (DEMec). A sessão será moderada pelo Prof. Pedro Diniz (DEI).

Sobre a palestra:

“Artificial Intelligence/Machine Learning (AI/ML) has transformed hardware design, software systems, and system architectures. Emerging hardware for AI accelerators have become heterogeneous and complex, that traditional modeling methodologies, benchmarks, and metrics for prior systems may not work for assessing AI models and AI hardware. The single-most commonly used operation in AI is matrix multiplication. Hardware accelerators like GPUs have created Tensor Cores to support matrix multiplication. Google TPUs support matrix multiplication by the hardware systolic arrays. However, matrix multiplication cannot be a reliable benchmark for benchmarking, due to its high sensitivity to optimizations. The MLPerf consortium creates ML benchmarks, however those benchmarks are prohibitively difficult to manage for many small companies and academic researchers. What are good benchmarks for AI/ML? How can you evaluate AI hardware in pre-silicon and post-silicon stages? Complete system simulation was a popular mode of pre-silicon evaluation but prohibitively expensive. This talk will describe some of the opportunities and challenges when AI meets Performance Engineering.”

Sobre a Oradora:

“Lizy Kurian John is Truchard Foundation Chair in Engineering at the University of Texas at Austin. Her research interests include workload characterization, performance evaluation, and high performance architectures for emerging workloads. She is recipient of many awards including Joe J. King Professional Engineering Achievement Award (2023), and The Pennsylvania State University Outstanding Engineering Alumnus Award (2011). She has authored 3 books and has edited 4 books including a book on Computer Performance Evaluation and Benchmarking. She holds 18 US patents and is an IEEE Fellow (Class of 2009), ACM Fellow, AAAS Fellow and Fellow of the National Academy of Inventors (NAI).”

Agradecimentos: Lizy K. John é atualmente especialista Fulbright. A sua investigação é financiada, em parte, pelas bolsas n.º 2326894 e n.º 2425655 da Fundação Nacional de Ciência dos Estados Unidos (NSF), pela Semiconductor Research Corporation (SRC) task 3148.001 e pela bolsa do Programa de Aceleração de Investigação Aplicada da NVIDIA.

A palestra “Life Post Moore’s Law: The New Design Frontier” será apresentada pelo Prof. Mark Horowitz (Stanford University), no dia 27 de março, às 14:00, na sala I-105. A sessão será moderada pelo Prof. Pedro Diniz (DEI).

Sobre a Palestra:

“For over 50 years, information technology has relied upon Moore’s Law: providing, for the same cost, 2x the number of logic transistors that were possible a few years prior. For much of that time, the smaller devices also provided dramatic energy and performance improvement through Dennard Scaling, but that scaling ended over a decade ago. While technology scaling continues, per transistor cost is no longer scaling in the advanced nodes. In this post Moore’s Law reality, further price/performance improvement follows only from improving the efficiency of applications using innovative hardware and software techniques.

Unfortunately, this need for innovative system solutions runs smack into the enormous complexity of designing and debugging contemporary VLSI based hardware/software platforms; a task so large it has caused the industry to consolidate, moving it away from innovation. The result is a set of platforms aim at different computing markets. To overcome this challenge, we need to develop a new design approach and tools to enable small groups of application experts to selectively extend the performance of those successful platforms.

Like the ASIC revolution in the 1980s, the goal of this approach is to enable a new set of designers, then board level logic designers, now application experts, to leverage the power of customized silicon solutions. Like then, these tools won’t initially be useful for current chip designers, but over time will underly all designs. In the 1980s to provide access to logic designers, the key technologies were logic synthesis, simulation, and placement/routing of their designs to gate arrays and std cells. Today, the key is to realize you are creating an “app” for an existing platform, and not creating the system solution from scratch (which is both too expensive and error prone), and to leverage the fact that modern “chips” are made of many chiplets. The new approach must provide a design window familiar to application developers, with similar descriptive, performance tuning, and debug capabilities. These new tools will be tied to highly capable platforms that are used as the foundation, like the appStore model for mobile phones. This talk will try to convince you this might be possible, and where innovative design/tools are needed.”

Sobre o Orador:

“Professor Horowitz initially focused on designing high-performance digital systems by combining work in computer-aided design tools, circuit design, and system architecture. During this time, he built a number of early RISC microprocessors, and contributed to the design of early distributed shared memory multiprocessors. In 1990, Dr. Horowitz took leave from Stanford to help start Rambus Inc., a company designing high-bandwidth memory interface technology. After returning in 1991, his research group pioneered many innovations in high-speed link design, and many of today’s high speed link designs are designed by his former students or colleagues from Rambus.

In the 2000s he started a long collaboration with Prof. Levoy on computational photography, which included work that led to the Lytro camera, whose photographs could be refocused after they were captured. Dr. Horowitz’s current research interests are quite broad and span using EE and CS analysis methods to problems in neuro and molecular biology to creating new agile design methodologies for analog and digital VLSI circuits. He remains interested in learning new things, and building interdisciplinary teams.”