“Lecture DEI Series
Date: July 15th
Time: 11:00
Room: Auditório B – INESCTEC
Speaker: Cristina Silvano
Affiliation: Dept. of Electronics, Information and Bioengineering, Politecnico di Milano, Italy
Abstract
Several classes of applications can expose at runtime a set of software knobs (including application parameters and code transformations) to trade-off the quality of the results and the throughput. Resource management and application autotuning are key issues for enabling computing systems to adjust their behavior in the face of changing conditions, operating environments, usage contexts and resource availability while meeting energy-efficiency and Quality-of-Service requirements.
This talk will present dynamic autotuning techniques for the multi-objective optimization of applications to tune software knobs in an adaptive scenario to trade-off accuracy versus performance. Machine learning techniques are used to predict the system behavior based on a set of training data. The main challenge is to exploit design-time and run-time concepts to lead to an effective way of “self-aware” computing. The talk also presents the application of dynamic autotuning techniques to energy-efficient HPC systems.
Short Bio
Cristina Silvano is a Full Professor of Computer Engineering at the Politecnico di Milano, Dept. of Electronics, Information and Bioengineering. In 2017, she has been elevated IEEE Fellow “for contributions to energy-efficient computer architectures”. Her research focuses on computer architectures and Electronic Design Automation, with emphasis on power-aware design of embedded systems, design space exploration of energy-efficient computer architectures and application autotuning for manycore architectures and High-Performance Computing. She was Project Coordinator of three European projects: H2020-FET-HPC ANTAREX-671623 (2015-2018), FP7-2PARMA-248716 (2010-2013) and FP7-MULTICUBE-216693 (2008-2010). She is an active member of the scientific community and she regularly serves in several international program committees. She also organized 15 international conferences/workshops as Program Chair or General Chair. She is Associate Editor of ACM Trans. on Architecture and Code Optimization (TACO) and IEEE Trans. on Computers. She served as Independent Expert Reviewer for the European Commission and for several science foundations. Her scientific production consists of more than 160 publications.”

“Lecture DEI Series
Date: June 25th
Time: 14:00
Room: Auditório A – INESCTEC
Speaker: Walid A. Najjar
Affiliation: Department of Computer Science & Engineering University of California Riverside
Abstract
For over two decades the gap between processor and memory speeds has been the most daunting challenge in computer architecture. The advent of big data applications has exacerbated the problem. Traditional multi-core architecture mitigate memory latency through the use of massive cache hierarchies that take up over 80% of the chip area and a proportional percentage of the energy budget. However, big data applications exhibit very poor data locality and cannot benefits from large cache hierarchies. Such applications will be fully impacted by memory latency. Hardware multithreaded architectures have the ability to mask memory latency by context switching between ready threads when a memory access is performed. Classical hardware multithreaded architectures, such as barrel processors (e.g. the UltraSparc and the Cray XMT), must maintain a full state for every thread which requires a lot of resources. FPGAs allow us the opportunity to configure custom or semi-custom processing cores for specific applications.
In this talk I will describe the implementation of data processing applications on the latency masking Filament architecture using semi-custom data paths.
Short Bio
Walid A. Najjar is a Professor in the Department of Computer Science and Engineering at the University of California Riverside. His areas of research include computer architectures and compilers for parallel and high-performance computing, embedded systems, FPGA-based code acceleration and reconfigurable computing.
Walid received a B.E. in Electrical Engineering from the American University of Beirut in 1979, and the M.S. and Ph.D. in Computer Engineering from the University of Southern California in 1985 and 1988 respectively. From 1989 to 2000 he was on the faculty of the Department of Computer Science at Colorado State University, before that he was with the USC-Information Sciences Institute. He was elected Fellow of the IEEE and the AAAS.”