PhD Defense in Digital Media: ”New Strategies and User-Generated Content in the Public Service Media News in the Digital World – The Portuguese Case”

Candidate:  Daniel dos Santos Catalão

Date, Time and Place

15th of December,14:30, Sala de Atos da Faculdade de Engenharia da Universidade do Porto

 

President of the Jury

Doutor António Fernando Vasconcelos Cunha Castro Coelho, Professor Associado com Agregação da FEUP

Members

Doutor Francisco Rui Nunes Cádima, Professor Catedrático (aposentado) da Faculdade de Ciências Sociais e Humanas da Universidade Nova de Lisboa;

Doutora Felisbela Maria Carvalho Lopes, Professora Associada com Agregação do Instituto de Ciências Sociais da Universidade do Minho;

Doutora Catarina Sofia Lourenço Rodrigues, Professora Auxiliar da Faculdade de Ciências Sociais e Humanas da Universidade dos Açores;

Doutor Fernando António Dias Zamith Silva, Professor Auxiliar do Departamento de Ciências da Comunicação e da Informação da Faculdade de Letras da Universidade do Porto (Coorientador);

Doutor Sérgio Sobral Nunes, Professor Auxiliar do Departamento de Engenharia Informática da Faculdade de Engenharia da Universidade do Porto.

Streaming via YouTube

Dealing with memory latency in the age of big data

Lecture DEI Series
Date: June 25th
Time: 14:00
Room: Auditório A – INESCTEC
Speaker: Walid A. Najjar
Affiliation: Department of Computer Science & Engineering University of California Riverside
Abstract
For over two decades the gap between processor and memory speeds has been the most daunting challenge in computer architecture. The advent of big data applications has exacerbated the problem. Traditional multi-core architecture mitigate memory latency through the use of massive cache hierarchies that take up over 80% of the chip area and a proportional percentage of the energy budget. However, big data applications exhibit very poor data locality and cannot benefits from large cache hierarchies. Such applications will be fully impacted by memory latency. Hardware multithreaded architectures have the ability to mask memory latency by context switching between ready threads when a memory access is performed. Classical hardware multithreaded architectures, such as barrel processors (e.g. the UltraSparc and the Cray XMT), must maintain a full state for every thread which requires a lot of resources. FPGAs allow us the opportunity to configure custom or semi-custom processing cores for specific applications.
In this talk I will describe the implementation of data processing applications on the latency masking Filament architecture using semi-custom data paths.
Short Bio
Walid A. Najjar is a Professor in the Department of Computer Science and Engineering at the University of California Riverside. His areas of research include computer architectures and compilers for parallel and high-performance computing, embedded systems, FPGA-based code acceleration and reconfigurable computing.
Walid received a B.E. in Electrical Engineering from the American University of Beirut in 1979, and the M.S. and Ph.D. in Computer Engineering from the University of Southern California in 1985 and 1988 respectively. From 1989 to 2000 he was on the faculty of the Department of Computer Science at Colorado State University, before that he was with the USC-Information Sciences Institute. He was elected Fellow of the IEEE and the AAAS.”

StepTalks2019: Software Engineering, Data protection, Privacy and Cybersafety

Today, Portuguese and international companies based in Portugal/South Europe have demonstrated an ability to react, indicating a growing concern to adopt good International practices in software engineering, as a way to foster their capabilities for their sustained growth, higher competitiveness and internationalization, also complying with the latest European/international legislation on data privacy and protection thus increasing their level of compliance and facilitating access to new markets, both in Portugal and internationally to their global base of customers.
 
Steptalks is back for a renewed edition and, motivated by these themes, intends to bring together specialists in a wide range of areas such as Software Engineering & Industry 4.0 as well as Data Protection, Privacy and Cybersecurity (including Blockchain). This way, the latest trends focusing on improving engineering processes and privacy / data protection can be shared with our audience.
 
Pedro Castro Henriques – Strongstep (Organizing Chair)
João Pascoal Faria – FEUP (Program Chair)
Raul Moreira Vidal – FEUP (Program Co-Chair)
Juan Garate – Tecnalia (Program Co-Chair)

Incentive Award 2019: Pedro Moás

Pedro Moás é um jovem portuense que frequenta o Mestrado Integrado em Engenharia Informática e Computação da Faculdade de Engenharia da U.Porto (FEUP). No ano letivo de 2017/18, terminou o seu primeiro ano de curso com a média final de 19,05 valores, facto que o levou a ser distinguido pela U.Porto com um Prémio Incentivo 2019, juntamente com os outros 21 alunos que mais se notabilizaram nas várias faculdades da U.Porto. É o próprio que enumera os fatores que explicam o seu sucesso no ano de estreia.
Para além do esforço pessoal que este prémio lhe reconhece, atribui também parte do mérito ao trabalho dos docentes da FEUP, que “sempre se mostraram disponíveis para esclarecer a matéria, dentro e fora de aulas, quer por e-mail, quer durante o horário de atendimento” e ao primeiro momento de contacto com a faculdade, ou seja, a semana de integração de novos alunos, que considera ter sido “bastante positiva” no sentido de “introduzir os estudantes ao ambiente da faculdade”. A nível pessoal, confessa que outro aspeto que o beneficiou grandemente foi a sensação de “maior autonomia” em relação ao ensino secundário, que experimentou na Universidade.
Há, porém, um aspeto que Pedro desejava ver melhorado na U.Porto – o sistema SIGARRA. “Precisa de ver melhorada a sua organização”, afirma Pedro Moás. “Ao longo deste ano, tenho visto vários alunos a salientar este aspeto, que pode prejudicar os estudantes que ainda não estão habituados a esta estrutura, por vezes confusa.”
No 108.º aniversário da instituição, o futuro engenheiro deseja o melhor para a U.Porto e que esta “continue a incentivar os novos alunos com iniciativas como esta.”

INESC TEC and FEUP bring National Robotics Festival to Gondomar

The National Robotics Festival arrives at the Gondomar Multipurpose Pavilion from April 26-28. In addition to about 500 participants, national and international, about 5,000 visitors are expected to attend robotic competitions and the exhibition of projects developed by various robotics clubs at the national level. More information, click here.

FEUP professor makes an innovative 360º video documentary

António Baia Reis, a professor from the Department of Computer Engineering and student of the Doctoral Program in Digital Media of the Oporto Engineering Faculty  (FEUP), will present, on May 2, at 14:30, at the Madeira Press Museum, ‘Bailinha – o Mestre Calafate’, a 360° video documentary that uses innovative technologies called ‘immersive’. More information, click  here.