The talk, entitled “Hybrid neural systems: neuromorphic computing for real-time control of brain activity“, will be given on 15 June at 2:00 pm in room I-105. Henrique Lopes Cardoso (DEI) will chair the session.

Abstract:

The brain is a powerful model for fast, adaptive and energy-efficient information processing. Translating these principles into computing systems is a major challenge with direct relevance for the next generation of intelligent neural interfaces. In this talk I will present work from my research group where we developed a hybrid neural system combining biological neurons with neuromorphic hardware, where artificial spiking neurons process ongoing brain activity in real time. By converting biological signals into spike-based representations, we trained spiking neural networks (SNNs) to identify short-lived electrophysiological patterns and deployed them on neuromorphic hardware. This system was integrated with open-source electrophysiology tools to create a closed-loop pipeline capable of detecting ongoing brain states and triggering targeted stimulation with low latency. Using this approach, we show that hybrid systems linking artificial and biological neurons can support real-time interaction with living neural circuits. These results provide a proof-of-concept for accessible neuromorphic neural interfaces and open new possibilities for adaptive, low-power and biologically inspired computing technologies.

About the Speaker:

Paulo Aguiar graduated in Physics (U. Lisbon, PT), and completed his PhD in Computational Neuroscience at the Institute for Adaptive and Neural Computation (U. Edinburgh, UK). Since 2016, he leads the Neuroengineering and Computational Neuroscience Lab (i3S-UPorto, PT). His group uses a bottom-up approach, focusing on understanding how neural circuits process and store information. The team combines expertise in neurobiology, advanced analytical methods and computational models, to reveal and repair neural function. He has already been the (co)PI/Task Leader in 20+ national and international research projects obtained through competitive calls.

The talk entitled “nanoML: Pushing the Limits of Edge AI with Weightless Neural Networks”, will be given by Prof. Lizy Kurian John (University of Texas at Austin) on 6 May at 2.30 pm in room I-105. The session will be moderated by Prof. Pedro Diniz (DEI).

About the Talk:

“Mainstream artificial neural network models, such as Deep Neural Networks (DNNs) are computation-heavy and energy-hungry. Weightless Neural Networks (WNNs) are natively built with RAM-based neurons and represent an entirely distinct type of neural network computing compared to DNNs. WNNs are extremely low-latency, low-energy, and suitable for efficient, accurate, edge inference. The WNN approach derives an implicit inspiration from the decoding process observed in the dendritic trees of biological neurons, making neurons based on Random Access Memories (RAMs) and/or Lookup Tables (LUTs) ready-to-deploy neuromorphic digital circuits. WNNs are a natural fit for edge AI due to the low area, energy and latency properties offered by them. This talk will describe the state of the art of Weightless Neural Networks, and their applications for edge inferencing.”

About the Speaker:

“Lizy Kurian John is Truchard Foundation Chair in Engineering at the University of Texas at Austin. Her research interests include workload characterization, performance evaluation, and high performance architectures for emerging workloads. She is recipient of many awards including Joe J. King Professional Engineering Achievement Award (2023), and The Pennsylvania State University Outstanding Engineering Alumnus Award (2011). She has authored 3 books and has edited 4 books including a book on Computer Performance Evaluation and Benchmarking. She holds 18 US patents and is an IEEE Fellow (Class of 2009), ACM Fellow, AAAS Fellow and Fellow of the National Academy of Inventors (NAI).”

Acknowledgement: Lizy K. John is currently a Fulbright Specialist. Her research is supported in part by the Unites States National Science Foundation (NSF) Grants #2326894, #2425655, Semiconductor Research Corporation (SRC) Task 3148.001, and NVIDIA Applied Research Accelerator Program Grant.

The talk entitled “When AI meets Performance Engineering: Challenges and Opportunities”, will be given by Prof. Lizy Kurian John (University of Texas at Austin) on 29 April, at 2.30 pm, in room L119 (DEMec). The session will be moderated by Prof. Pedro Diniz (DEI).

About the Talk:

“Artificial Intelligence/Machine Learning (AI/ML) has transformed hardware design, software systems, and system architectures. Emerging hardware for AI accelerators have become heterogeneous and complex, that traditional modeling methodologies, benchmarks, and metrics for prior systems may not work for assessing AI models and AI hardware. The single-most commonly used operation in AI is matrix multiplication. Hardware accelerators like GPUs have created Tensor Cores to support matrix multiplication. Google TPUs support matrix multiplication by the hardware systolic arrays. However, matrix multiplication cannot be a reliable benchmark for benchmarking, due to its high sensitivity to optimizations. The MLPerf consortium creates ML benchmarks, however those benchmarks are prohibitively difficult to manage for many small companies and academic researchers. What are good benchmarks for AI/ML? How can you evaluate AI hardware in pre-silicon and post-silicon stages? Complete system simulation was a popular mode of pre-silicon evaluation but prohibitively expensive. This talk will describe some of the opportunities and challenges when AI meets Performance Engineering.”

About the Speaker:

“Lizy Kurian John is Truchard Foundation Chair in Engineering at the University of Texas at Austin. Her research interests include workload characterization, performance evaluation, and high performance architectures for emerging workloads. She is recipient of many awards including Joe J. King Professional Engineering Achievement Award (2023), and The Pennsylvania State University Outstanding Engineering Alumnus Award (2011). She has authored 3 books and has edited 4 books including a book on Computer Performance Evaluation and Benchmarking. She holds 18 US patents and is an IEEE Fellow (Class of 2009), ACM Fellow, AAAS Fellow and Fellow of the National Academy of Inventors (NAI).”

Acknowledgement: Lizy K. John is currently a Fulbright Specialist. Her research is supported in part by the Unites States National Science Foundation (NSF) Grants #2326894, #2425655, Semiconductor Research Corporation (SRC) Task 3148.001, and NVIDIA Applied Research Accelerator Program Grant.

The talk “Life Post Moore’s Law: The New Design Frontier” will be given by Prof. Mark Horowitz (Stanford University) on March 27th, at 14:00, in room I-105. The session will be chaired by Prof. Pedro Diniz (DEI).

About the Talk:

“For over 50 years, information technology has relied upon Moore’s Law: providing, for the same cost, 2x the number of logic transistors that were possible a few years prior. For much of that time, the smaller devices also provided dramatic energy and performance improvement through Dennard Scaling, but that scaling ended over a decade ago. While technology scaling continues, per transistor cost is no longer scaling in the advanced nodes. In this post Moore’s Law reality, further price/performance improvement follows only from improving the efficiency of applications using innovative hardware and software techniques.

Unfortunately, this need for innovative system solutions runs smack into the enormous complexity of designing and debugging contemporary VLSI based hardware/software platforms; a task so large it has caused the industry to consolidate, moving it away from innovation. The result is a set of platforms aim at different computing markets. To overcome this challenge, we need to develop a new design approach and tools to enable small groups of application experts to selectively extend the performance of those successful platforms.

Like the ASIC revolution in the 1980s, the goal of this approach is to enable a new set of designers, then board level logic designers, now application experts, to leverage the power of customized silicon solutions. Like then, these tools won’t initially be useful for current chip designers, but over time will underly all designs. In the 1980s to provide access to logic designers, the key technologies were logic synthesis, simulation, and placement/routing of their designs to gate arrays and std cells. Today, the key is to realize you are creating an “app” for an existing platform, and not creating the system solution from scratch (which is both too expensive and error prone), and to leverage the fact that modern “chips” are made of many chiplets. The new approach must provide a design window familiar to application developers, with similar descriptive, performance tuning, and debug capabilities. These new tools will be tied to highly capable platforms that are used as the foundation, like the appStore model for mobile phones. This talk will try to convince you this might be possible, and where innovative design/tools are needed.”

About the Speaker:

“Professor Horowitz initially focused on designing high-performance digital systems by combining work in computer-aided design tools, circuit design, and system architecture. During this time, he built a number of early RISC microprocessors, and contributed to the design of early distributed shared memory multiprocessors. In 1990, Dr. Horowitz took leave from Stanford to help start Rambus Inc., a company designing high-bandwidth memory interface technology. After returning in 1991, his research group pioneered many innovations in high-speed link design, and many of today’s high speed link designs are designed by his former students or colleagues from Rambus.

In the 2000s he started a long collaboration with Prof. Levoy on computational photography, which included work that led to the Lytro camera, whose photographs could be refocused after they were captured. Dr. Horowitz’s current research interests are quite broad and span using EE and CS analysis methods to problems in neuro and molecular biology to creating new agile design methodologies for analog and digital VLSI circuits. He remains interested in learning new things, and building interdisciplinary teams.”

The talk “Accelerating ML for Science Applications” will be presented by Prof. Seda Ogrenci (McCormick School of Engineering, Northwestern University) on March the 12th, at 11:00, in room I-105. The session will be moderated by Tiago Carvalho (DEI).

About the Talk:

“Emerging open-source tools and methodologies targeting reconfigurable fabrics hold significant promise for lowering barriers to research, education, and innovation. There are exciting developments in diverse domains where such benefits are demonstrated. This talk will review active domains with needs and applications for real-time ultra low latency ML hardware and how open-source tools need to evolve to provide a multitude of features to enable design of hardware efficient and adaptive ML. As part of this discussion, examples of research directions in adaptive and resilient ML hardware synthesis flows developed in Dr. Ogrenci’s lab will presented.”

About the Speaker:

Seda Ogrenci is a Professor in the Department of Electrical and Computer Engineering (ECE), and in the Department of Computer Science (CS). She is the Director of the Computer Engineering Division of ECE. She has received her PhD degree in Computer Science from the University of California-Los Angeles. She is the co-author of over 140 peer reviewed publications and twelve patents on the subjects of Electronic Design Automation, Reconfigurable Computing, Thermal-Aware High Performance Computing, Computer Architecture, and Instrumentation for Real-Time ML for Experimental Sciences. She is the author of the book: Heat Management in Integrated Circuits: On-chip and system-level monitoring and cooling (Materials, Circuits and Devices). Seda Ogrenci serves on the editorial boards of the IEEE Transactions on Computer Aided Design and ACM Transactions of Reconfigurable Technology and Systems.

The talk entitled “The Geometry of Logic” will be presented by Prof. Cristina (Crista) Videira Lopes, from the University of California, next Wednesday, February the 25th, at 14:00, in room I-105. The session will be moderated by Prof. Rui Maranhão (DEI).

About the talk:

“Large Language Models (LLMs) exhibit surprising reasoning capabilities, yet the internal mechanisms driving these behaviors remain opaque. We hypothesize that this emergence may be driven by soft stratification: the spontaneous (and inefficient) discovery of orthogonal subspaces that separate control flow from data flow. To explore this, we introduce the STRAT architecture (STratified Registers And Types), which imposes hard stratification by explicitly partitioning the embedding space.
We evaluate STRAT on algorithmic tasks requiring precise logical manipulation. Despite having no pre-programmed knowledge of those tasks, the model spontaneously discovers interpretable
geometric topologies (e.g., antipodal operator separation) to solve the tasks. These geometric constraints also yield extreme data efficiency: models converge to the correct logical rules of arithmetic from as few as N=10 training examples. These results suggest that the stratification of the embedding space is a promising geometric substrate for neural logic.”

About the Speaker:

Cristina (Crista) Videira Lopes is a Professor of Informatics in the School of Information and Computer Sciences at the University of California, Irvine. Her research focuses on programming and software engineering for large-scale data and systems. Early in her career, she was a founding member of the team at Xerox PARC that developed Aspect-Oriented Programming. Along with her research program, she is also a prolific software developer. Her open source contributions include being one of the core developers of OpenSimulator, a virtual world server. She is also a founder and consultant of Encitra, a company specializing in online virtual reality for early-stage sustainable urban redevelopment projects. Her book “Exercises in Programming Style” has gained rave reviews, including being chosen as “Notable Book” by the ACM Best of Computing reviews. She has a PhD from Northeastern University, and MS and BS degrees from Instituto Superior Tecnico in Portugal. She is the recipient of several National Science Foundation grants, including a prestigious CAREER Award. She claims to be the only person in the world who is both an ACM Distinguished Scientist and Ohloh Kudos Rank 9.

The talk entitled “The impact of link recommendation algorithms on human social dynamics” will be presented by Prof. Fernando Pascoal dos Santos (University of Amsterdam) on March the 20th, at 11:00, in room I-105. The session will be moderated by Prof. Sérgio Nunes (DEI).

About the Talk:

“Online social networks increasingly shape human beliefs and behavior. In these environments, algorithms to personalize contents and provide recommendations are pervasive. Link recommendation algorithms are implemented to recommend new connections to online platforms users, based on supposed familiarity, similar interests, or the potential to serve as a source of useful information. These algorithms influence the evolution of social networks, yet their long-term impacts on human social dynamics remain unclear. In this talk, I will discuss models to study such effects. I will discuss how algorithmic link recommendations interplay with opinion dynamics, and the potential long-term impacts of such algorithms on polarization. I will also discuss methods based on agentic multi-systems, powered by LLMs, to test social media interventions aiming at mitigating polarized dynamics. We will observe that preferentially establishing links with structurally similar nodes (i.e., sharing many neighbors) results in network topologies that are amenable to opinion polarization.”

About the Speaker:

Fernando P. Santos is an Associate Professor at the University of Amsterdam. He is a member of the Socially Intelligent Artificial Systems group, where he leads the Prosocial Dynamics Lab. Fernando’s research lies at the interface of AI and Complex Systems: he is interested in understanding behavioral dynamics in systems of adaptive learning agents and designing (pro)Social AI. Previously, Fernando was a James S. McDonnell Postdoctoral Fellow at Princeton University. He completed his PhD in Computer Science and Engineering at Instituto Superior Técnico with Francisco C. Santos, Jorge M. Pacheco, and Ana Paiva. Fernando is an ELLIS Scholar and member of the board of directors of the International Foundation for Autonomous Agents and Multiagent Systems. He was awarded an ERC Starting Grant to study the impact of link-recommendation algorithms on human behavioural dynamics.

The talk entitled “High Performance Computing for Bioinformatics Applications: the Quest for Performance” will be presented by Prof. Alba Alves de Melo (University of Brasilia) and will take place on the 20th February, at 14:30, in room B018. Prof. João Bispo (DEI) will moderate the session.

About the Talk:

“Bioinformatics applications are often computationally intensive, making High-Performance Computing (HPC) highly desirable. In this lecture, I will present parallel bioinformatics applications developed for High-Performance Computing (HPC) environments over the years by my research group at the LAICO Laboratory at the University of Brasília. The following will be addressed: (a) parallel applications for exact pairwise comparison of long biological sequences in clusters of GPUs (Graphics Processing Units) and CPUs; (b) exact multiple sequence alignment applications for multithreaded architectures; (c) exact RNA secondary structure prediction (folding and alignment) in GPU; and (d) heuristic protein folding in a supercomputer. Finally, a framework for executing scientific workflows in the HPC cloud will be presented.”

About the Speaker:

Alba Cristina Magalhaes Alves de Melo obtained her PhD in Computer Science from the Institut National Polytechnique de Grenoble (INPG), France, in 1996. Since 1997, she is with the Department of Computer Science at the University of Brasilia, Brazil, where she is now Full Professor. Prof. Melo is IEEE Senior Member, Vice-Coordinator of the IEEE Technical Community of Parallel Processing (TCPP) since 2024 and Member of the Counselling Committee in Computer Science for CNPq/Brazil since 2025. Prof. Melo received the following awards: 2023 IEEE Technical Committee on Parallel Processing (TCPP) Outstanding Service and Contributions Award; 2019 Wilkes Award for the Best Paper Published in The Computer Journal in 2018, Oxford University Press (joint work with the UPC/BSC team); 2016 Award for Advisor of the Best PhD Thesis in Computer Science in Brazil (Premio Capes de Tese).
She is Associate Editor-in-Chief of the Applications section of the Journal of Parallel and Distributed Systems (JPDC). She is also Associate Editor of many prestigious journals such as IEEE Transactions on Computers, IEEE Transactions on Parallel and Distributed Systems, ACM Computing Surveys and Future Generation Computer Systems. She was Co-General Chair of IEEE International Parallel and Distributed Processing Symposium (IPDPS) 2024. She has served as Program Chair or Track Chair of many prestigious conferences in high performance computing such as IPDPS, Supercomputing (SC), Euro-Par, HiPEAC, Cluster, ICPP, SBAC-PAD and HiPC. Prof. Melo’s research group has established long lasting collaborations with research teams from the University of Ottawa, Canada (since 2005); INRIA/Saclay and Mines Paris Tech, France (since 2011); Universitat Politecnica de Catalunya/ Barcelona Supercomputing Center (UPC/BSC), Spain (since 2012); and University of Copenhagen, Denmark (since 2017). Her research interests are high performance computing, bioinformatics and cloud computing.

The talk “NextGen Accelerators: Flexible, Scalable, Efficient – Together” will be presented by Prof. Pedro Trancoso (Chalmers University of Technology) on the 19th February, at 11:00, in room B008. Prof. Diniz (DEI) will be responsible for moderating the event.

About the Talk:

“For a long time, computer systems have been built around an increasingly powerful general-purpose processor. Nevertheless, at some point these monolithic super chips were not able to deliver the expected additional performance due to limitations such as design complexity and power density.
The decline of the monolithic processor gave way to new architectures. With efficiency as a main goal, domain-specific architectures, also known as accelerators, started playing an important role. The realization that one-size does not fit all resulted in an explosion of diverse accelerators for different applications and purposes, from both research and industry.
Designers of these accelerators are usually faced with the tradeoff between a generic architecture that will stand the test of time and an application-dedicated architecture that is very efficient. We want both! As such, we focus on the design of building blocks for the next generation of accelerators. These blocks are efficient but at the same time can be combined in different ways to achieve the required flexibility and scalability. In this talk I will present some of our recent research results towards this goal.”

About the Speaker:

Pedro Trancoso is a Full Professor at the Department of Computer Science and Engineering (CSE) of the Chalmers University of Technology, Sweden. He has an engineering degree from Instituto Superior Técnico (IST) (1993), Portugal and a MSc and PhD (1998) from the University of Illinois at Urbana-Champaign, U.S.A. His research interests are in computer architecture (memory hierarchy, multicore processors, reconfigurable computing, and energy efficiency) with main focus on the hardware acceleration for emerging applications such as machine learning. He is currently actively collaborating in several EU research projects (VEDLIoT, eProcessor and EPI SGA2) and SSF Swedish research projects (PRIDE, QuantumStack, AutoPIM), as well as the EUMaster4HPC EU Masters project on HPC. He is also the director of the Masters programme on High-Performance Computer systems (MPHPC) at Chalmers since its start in 2019.

The talk entitled “Safer Software with Liquid Types” will be presented by Prof. Alcides Fonseca on February 4th at 15:00, in room B006, moderated by Prof. José Campos (DEI).

About the Talk:

“In a world where LLM-generated code is being produced at a faster pace than human written code, verification is more important than ever. Liquid Types (refining types with logical predicates, e.g. {x:Int | x > 10}) have been around for 17 years now but, despite their many applications, they haven’t taken off. In this talk we will answer why (PLDI’25), based on user interviews we conducted, relating them to other verification tools such as Interactive Theorem Provers and Design-by-Contract approaches like Dafny. Finally, we will see how our research group is addressing those challenges in both LiquidJava and Aeon.”

About the Speaker:

Alcides Fonseca is an Associate Professor at the University of Lisbon, Portugal, where he leads the Reliable Software Systems research line. In parallel to his day job as an Associate Professor at U. Lisbon, Alcides has been working for and with several startups over the years, including founding a junior company. In any of those jobs, Alcides uses a mix of programming languages (Python, Haskell, Lean, Scala) and some that his research group have developed, like the Aeon programming language that automatically generates code for you, based on Genetic Programming and Liquid Types.