The talk, entitled “Hybrid neural systems: neuromorphic computing for real-time control of brain activity“, will be given on 15 June at 2:00 pm in room I-105. Henrique Lopes Cardoso (DEI) will chair the session.

Abstract:

The brain is a powerful model for fast, adaptive and energy-efficient information processing. Translating these principles into computing systems is a major challenge with direct relevance for the next generation of intelligent neural interfaces. In this talk I will present work from my research group where we developed a hybrid neural system combining biological neurons with neuromorphic hardware, where artificial spiking neurons process ongoing brain activity in real time. By converting biological signals into spike-based representations, we trained spiking neural networks (SNNs) to identify short-lived electrophysiological patterns and deployed them on neuromorphic hardware. This system was integrated with open-source electrophysiology tools to create a closed-loop pipeline capable of detecting ongoing brain states and triggering targeted stimulation with low latency. Using this approach, we show that hybrid systems linking artificial and biological neurons can support real-time interaction with living neural circuits. These results provide a proof-of-concept for accessible neuromorphic neural interfaces and open new possibilities for adaptive, low-power and biologically inspired computing technologies.

About the Speaker:

Paulo Aguiar graduated in Physics (U. Lisbon, PT), and completed his PhD in Computational Neuroscience at the Institute for Adaptive and Neural Computation (U. Edinburgh, UK). Since 2016, he leads the Neuroengineering and Computational Neuroscience Lab (i3S-UPorto, PT). His group uses a bottom-up approach, focusing on understanding how neural circuits process and store information. The team combines expertise in neurobiology, advanced analytical methods and computational models, to reveal and repair neural function. He has already been the (co)PI/Task Leader in 20+ national and international research projects obtained through competitive calls.

The talk entitled “nanoML: Pushing the Limits of Edge AI with Weightless Neural Networks”, will be given by Prof. Lizy Kurian John (University of Texas at Austin) on 6 May at 2.30 pm in room I-105. The session will be moderated by Prof. Pedro Diniz (DEI).

About the Talk:

“Mainstream artificial neural network models, such as Deep Neural Networks (DNNs) are computation-heavy and energy-hungry. Weightless Neural Networks (WNNs) are natively built with RAM-based neurons and represent an entirely distinct type of neural network computing compared to DNNs. WNNs are extremely low-latency, low-energy, and suitable for efficient, accurate, edge inference. The WNN approach derives an implicit inspiration from the decoding process observed in the dendritic trees of biological neurons, making neurons based on Random Access Memories (RAMs) and/or Lookup Tables (LUTs) ready-to-deploy neuromorphic digital circuits. WNNs are a natural fit for edge AI due to the low area, energy and latency properties offered by them. This talk will describe the state of the art of Weightless Neural Networks, and their applications for edge inferencing.”

About the Speaker:

“Lizy Kurian John is Truchard Foundation Chair in Engineering at the University of Texas at Austin. Her research interests include workload characterization, performance evaluation, and high performance architectures for emerging workloads. She is recipient of many awards including Joe J. King Professional Engineering Achievement Award (2023), and The Pennsylvania State University Outstanding Engineering Alumnus Award (2011). She has authored 3 books and has edited 4 books including a book on Computer Performance Evaluation and Benchmarking. She holds 18 US patents and is an IEEE Fellow (Class of 2009), ACM Fellow, AAAS Fellow and Fellow of the National Academy of Inventors (NAI).”

Acknowledgement: Lizy K. John is currently a Fulbright Specialist. Her research is supported in part by the Unites States National Science Foundation (NSF) Grants #2326894, #2425655, Semiconductor Research Corporation (SRC) Task 3148.001, and NVIDIA Applied Research Accelerator Program Grant.

The talk entitled “When AI meets Performance Engineering: Challenges and Opportunities”, will be given by Prof. Lizy Kurian John (University of Texas at Austin) on 29 April, at 2.30 pm, in room L119 (DEMec). The session will be moderated by Prof. Pedro Diniz (DEI).

About the Talk:

“Artificial Intelligence/Machine Learning (AI/ML) has transformed hardware design, software systems, and system architectures. Emerging hardware for AI accelerators have become heterogeneous and complex, that traditional modeling methodologies, benchmarks, and metrics for prior systems may not work for assessing AI models and AI hardware. The single-most commonly used operation in AI is matrix multiplication. Hardware accelerators like GPUs have created Tensor Cores to support matrix multiplication. Google TPUs support matrix multiplication by the hardware systolic arrays. However, matrix multiplication cannot be a reliable benchmark for benchmarking, due to its high sensitivity to optimizations. The MLPerf consortium creates ML benchmarks, however those benchmarks are prohibitively difficult to manage for many small companies and academic researchers. What are good benchmarks for AI/ML? How can you evaluate AI hardware in pre-silicon and post-silicon stages? Complete system simulation was a popular mode of pre-silicon evaluation but prohibitively expensive. This talk will describe some of the opportunities and challenges when AI meets Performance Engineering.”

About the Speaker:

“Lizy Kurian John is Truchard Foundation Chair in Engineering at the University of Texas at Austin. Her research interests include workload characterization, performance evaluation, and high performance architectures for emerging workloads. She is recipient of many awards including Joe J. King Professional Engineering Achievement Award (2023), and The Pennsylvania State University Outstanding Engineering Alumnus Award (2011). She has authored 3 books and has edited 4 books including a book on Computer Performance Evaluation and Benchmarking. She holds 18 US patents and is an IEEE Fellow (Class of 2009), ACM Fellow, AAAS Fellow and Fellow of the National Academy of Inventors (NAI).”

Acknowledgement: Lizy K. John is currently a Fulbright Specialist. Her research is supported in part by the Unites States National Science Foundation (NSF) Grants #2326894, #2425655, Semiconductor Research Corporation (SRC) Task 3148.001, and NVIDIA Applied Research Accelerator Program Grant.

The talk “Life Post Moore’s Law: The New Design Frontier” will be given by Prof. Mark Horowitz (Stanford University) on March 27th, at 14:00, in room I-105. The session will be chaired by Prof. Pedro Diniz (DEI).

About the Talk:

“For over 50 years, information technology has relied upon Moore’s Law: providing, for the same cost, 2x the number of logic transistors that were possible a few years prior. For much of that time, the smaller devices also provided dramatic energy and performance improvement through Dennard Scaling, but that scaling ended over a decade ago. While technology scaling continues, per transistor cost is no longer scaling in the advanced nodes. In this post Moore’s Law reality, further price/performance improvement follows only from improving the efficiency of applications using innovative hardware and software techniques.

Unfortunately, this need for innovative system solutions runs smack into the enormous complexity of designing and debugging contemporary VLSI based hardware/software platforms; a task so large it has caused the industry to consolidate, moving it away from innovation. The result is a set of platforms aim at different computing markets. To overcome this challenge, we need to develop a new design approach and tools to enable small groups of application experts to selectively extend the performance of those successful platforms.

Like the ASIC revolution in the 1980s, the goal of this approach is to enable a new set of designers, then board level logic designers, now application experts, to leverage the power of customized silicon solutions. Like then, these tools won’t initially be useful for current chip designers, but over time will underly all designs. In the 1980s to provide access to logic designers, the key technologies were logic synthesis, simulation, and placement/routing of their designs to gate arrays and std cells. Today, the key is to realize you are creating an “app” for an existing platform, and not creating the system solution from scratch (which is both too expensive and error prone), and to leverage the fact that modern “chips” are made of many chiplets. The new approach must provide a design window familiar to application developers, with similar descriptive, performance tuning, and debug capabilities. These new tools will be tied to highly capable platforms that are used as the foundation, like the appStore model for mobile phones. This talk will try to convince you this might be possible, and where innovative design/tools are needed.”

About the Speaker:

“Professor Horowitz initially focused on designing high-performance digital systems by combining work in computer-aided design tools, circuit design, and system architecture. During this time, he built a number of early RISC microprocessors, and contributed to the design of early distributed shared memory multiprocessors. In 1990, Dr. Horowitz took leave from Stanford to help start Rambus Inc., a company designing high-bandwidth memory interface technology. After returning in 1991, his research group pioneered many innovations in high-speed link design, and many of today’s high speed link designs are designed by his former students or colleagues from Rambus.

In the 2000s he started a long collaboration with Prof. Levoy on computational photography, which included work that led to the Lytro camera, whose photographs could be refocused after they were captured. Dr. Horowitz’s current research interests are quite broad and span using EE and CS analysis methods to problems in neuro and molecular biology to creating new agile design methodologies for analog and digital VLSI circuits. He remains interested in learning new things, and building interdisciplinary teams.”

The talk “Accelerating ML for Science Applications” will be presented by Prof. Seda Ogrenci (McCormick School of Engineering, Northwestern University) on March the 12th, at 11:00, in room I-105. The session will be moderated by Tiago Carvalho (DEI).

About the Talk:

“Emerging open-source tools and methodologies targeting reconfigurable fabrics hold significant promise for lowering barriers to research, education, and innovation. There are exciting developments in diverse domains where such benefits are demonstrated. This talk will review active domains with needs and applications for real-time ultra low latency ML hardware and how open-source tools need to evolve to provide a multitude of features to enable design of hardware efficient and adaptive ML. As part of this discussion, examples of research directions in adaptive and resilient ML hardware synthesis flows developed in Dr. Ogrenci’s lab will presented.”

About the Speaker:

Seda Ogrenci is a Professor in the Department of Electrical and Computer Engineering (ECE), and in the Department of Computer Science (CS). She is the Director of the Computer Engineering Division of ECE. She has received her PhD degree in Computer Science from the University of California-Los Angeles. She is the co-author of over 140 peer reviewed publications and twelve patents on the subjects of Electronic Design Automation, Reconfigurable Computing, Thermal-Aware High Performance Computing, Computer Architecture, and Instrumentation for Real-Time ML for Experimental Sciences. She is the author of the book: Heat Management in Integrated Circuits: On-chip and system-level monitoring and cooling (Materials, Circuits and Devices). Seda Ogrenci serves on the editorial boards of the IEEE Transactions on Computer Aided Design and ACM Transactions of Reconfigurable Technology and Systems.